1. Field of the Invention
The present invention relates to a logic IC, more particularly, to a logic IC with a memory embedded therein.
2. Description of the Related Art
There are some logic ICs each with an embedded memory wherein the memory is never directly accessed by another device external to the logic IC during its use in operations for directly writing and reading out data to and from the memory. It is necessary upon the completion of a process to manufacture such a logic IC into a product to test the logic circuit employed therein as well as the embedded memory.
A test of a logic circuit of an IC can be carried out by supplying an arbitrary signal to the logic circuit through a pin of the IC and observing a signal output by the logic circuit also through a pin of the IC.
As for a test of a memory embedded in the IC, signals such as address, control and data signals are supplied to the memory from a source external to the IC and a data signal output by the memory is fetched by an observing device also external to the IC. Since providing pins to the IC only for memory-test purposes will limit the enhancement of the degree of integration of the IC, however, pins for the logic circuit are also used for supplying the signals such as address, control and data signals and for observing the data signal in a memory test.
Speaking concretely, a selector is provided. When testing the embedded memory, the selector is put in a state that allows the memory to be accessed through the selector. In this way, the embedded memory can be tested. In normal usage, the selector is put in a state that prevents the embedded memory from being accessed from a device external to the IC. In this state, the external pins of the IC are virtually connected to the logic circuit only.
With such a scheme, some pins used for testing the embedded memory are shared by the logic circuit. As a result, the number of pins dedicated for test purposes only is relatively small.
Depending upon the number of pins for the logic circuit, however, test data generally can not be supplied and observed in some cases unless pins dedicated for test purposes are provided. For example, eight input pins and eight output pins are provided for test purposes involving eight-bit data. In this case, a total of 16 test pins which are required only during a test are not used at all in a normal operation. In the case of 16, 32 or 64-bit test data, a total of 32, 64 or 128 test pins which are not used at all in a normal operation need to be provided for test purposes only. In addition, in order to respond to a demand for an enhanced graphic performance for three-dimensional graphic applications for example, the IC is required to go multi-bit, giving rise to a problem that the number of test pins increases due to the multi-bit configuration, a problem that can no longer be overlooked.